(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a SONOS non-volatile memory device and a method of manufacturing the same.
(b) Description of the Related Art
Generally, since a non-volatile memory device has several merits, such as a small cell size, fast erasing and programming operation, and long-term capacity of data storage, then a non-volatile memory device is frequently used as a signaling transistor in a personal digital assistant (PDA), a digital camera, a personal communication system (PCS), and a smart card, or as a memory device as a substitute for a dynamic random access memory (DRAM).
Such non-volatile memory devices are classified into a floating-gate-based memory and a Metal Insulator Semiconductor (MIS) based memory.
A floating-gate-based memory device realizes its memory characteristics using a potential well. On the other hand, an MIS-based memory device having double or triple dielectric layers realizes its memory characteristics using a trap that exists at each interface between dielectric bulk, between dielectric layers, and between a dielectric layer and a semiconductor. Therefore, an MIS-based memory device is more applicable to low voltage and high speed than a floating-gate-based memory device.
As typical MIS-based memory devices, there are Metal Oxide Nitride Oxide Silicon (MONOS) and Silicon Oxide Nitride Oxide Silicon (SONOS) devices which are mainly used as Electrically Erasable Programmable Read Only Memory (EEPROMs).
When a programming operation in a MONOS or SONOS non-volatile memory device is performed, a threshold voltage is increased by trapping electrons within a trap site at a nitride layer through Fowler-Nordheim (FN) tunneling or direct tunneling. Similarly, in the case of an erasing operation therein, a threshold voltage is decreased by releasing electrons out to a substrate through FN tunneling, direct tunneling, or trap-assisted tunneling.
A conventional method of manufacturing a SONOS non-volatile memory device will hereinafter be described in detail with reference to FIG. 1A to FIG. 1E and FIG. 2A to FIG. 2E.
FIG. 1A to FIG. 1E and FIG. 2A to FIG. 2E are cross-sectional views and top plan views showing a conventional method of manufacturing a non-volatile memory device.
Referring to FIG. 1A and FIG. 2A, a mask pattern (not shown) comprised of a pad oxide layer and pad nitride layer is formed on a semiconductor substrate 110, and a trench (not shown) is formed by etching a portion of the substrate 110 exposed by a mask pattern. Subsequently, an oxide layer is deposited so as to fill the trench, and then an isolation layer 112 is formed by planarizing the oxide layer through a chemical mechanical polishing (CMP) process and by removing the mask pattern. Consequently, an active region 114 is defined on the semiconductor substrate 110 by forming the isolation layer 112.
Thereafter, although not shown, a well region and a threshold voltage adjusting layer are formed on the substrate 110 by performing ion implantation for a well and threshold voltage adjustment. Then, an ONO insulation layer 120 is formed by sequentially depositing a first oxide layer 122, a nitride layer 124, and a second oxide layer 126 on the substrate 110.
Referring to FIG. 1B and FIG. 2B, a gate 130 is formed by patterning a polysilicon layer (not shown) deposited on the insulation layer 120.
Referring to FIG. 1C and FIG. 2C, LDD (Lightly Doped Drain) regions 142 and 144 are formed in the active region 114 at both sides of the gate 130 by ion-implanting LDD ions into the substrate 110.
Referring to FIG. 1D and FIG. 2D, an insulation layer which is composed of an oxide layer, a nitride layer, or a composite layer thereof is deposited on an entire surface of the substrate 110, and then a spacer 150 is formed at both sidewalls of the gate 130 by performing blanket etching for the insulation layer to a degree that the gate 130 is exposed.
Subsequently, source and drain regions 162 and 164 are formed in the active region 114 at both sides of the spacer 150 by ion-implanting high concentration impurities into the substrate 110.
Referring to FIG. 1E and FIG. 2E, silicide layers 172, 174, and 176 are formed on the source and drain regions 162 and 164 and the gate 130 by performing a well-known salicide (self-aligned silicide) process, and then an interlayer insulation layer 180 is formed on the entire surface of the substrate 110. Subsequently, contact holes (not shown) are formed by etching the interlayer insulation layer 180 on the silicide layers 172, 174, and 176, and then conductive contact plugs 192, 194, and 196 are formed by filling the contact holes. The conductive contact plugs 192, 194, and 196 respectively contact the source and drain regions 162 and 164 and the gate 130 through the silicide layers 172, 174, and 176.
However, since a conventional method of manufacturing a non-volatile memory device has a limit for reducing a cell size while assuring storage capacities required for operations of devices, it is not easily applicable to higher integration of the semiconductor device.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form part of the prior art with respect to the present invention.